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| products and specifications discussed herein are subject to change by micron without notice. pdf: 09005aef80a41b59/zip: 09005aef811ba111 mt49h8m18c_1.fm - rev. f 11/04 en 1 ?2004 micron technology, inc. all rights reserved. 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii 288mb sio reduced latency (rldram ii) MT49H16M18C mt49h32m9c features ? 288mb 400 mhz ddr operation (800 mb/s/pin data rate) organization 16 meg x 18, 32 meg x 9 separate i/o 8 banks cyclic bank switching for maximum bandwidth reduced cycle time (20ns at 400 mhz) nonmultiplexed addresses (address multiplexing option available) sram-type interface read latency (rl), row cycle time, and burst sequence length balanced read and write latencies in order to optimize data bus utilization data mask for write commands differential input clocks (ck, ck#) differential input data clocks (dkx, dkx#) on-chip dll generates ck edge-aligned data and output data clock signals data valid signal (qvld) 32ms refresh (8k refresh for each bank; 64k refresh command must be issued in total each 32ms) 144-ball fbga package hstl i/o (1.5v or 1.8v nominal) 25 ? ?60 ? matched impedance outputs 2.5v v ext , 1.8v v dd , 1.5v or 1.8v v dd q i/o on-die termination (odt) r tt note: 1. contact micron for availability of lead-free products. options marking clock cycle timing 2.5ns (400 mhz) 3.3ns (300 mhz) 5ns (200 mhz) -25 -33 -5 configuration 16 meg x 18 32 meg x 9 MT49H16M18Cfm mt49h32m9cfm package 144-ball fbga (11mm x 18.5mm) fm bm (lead-free) 1 table 1: valid part numbers part number description MT49H16M18Cfm-xx 16 meg x 18 rldram ii mt49h32m9cfm-xx 32 meg x 9 rldram ii figure 1: 144-ball fbga
16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18ctoc.fm - rev. f 11/04 en 2 ?2004 micron technology, inc. all rights reserved. table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 programmable impedance output buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 clock considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 mode register set command (mrs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 write basic information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 read basic information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 auto refresh command (aref) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 on-die termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 operation with multiplexed addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 refresh command in multiplexed address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 ieee 1149.1 serial boundary scan (jtag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 disabling the jtag feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 test clock (tck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 test mode select (tms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 test data-in (tdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 test data-out (tdo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 performing a tap reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 tap registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 boundary scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 identification (id) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 tap instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 extest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 high-z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 sample/preload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 absolute maximum ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 data sheet designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18clof.fm - rev. f 11/04 en 3 ?2004 micron technology, inc. all rights reserved. list of figures figure 1: 144-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: functional block diag ram ? 16 meg x 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 3: 16 meg x 18 ball assignment (top view) 144-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 4: 32 meg x 9 ball assignment (top view) 144-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 5: clock/input data clock command/ad dress timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 6: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 7: clock input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 8: mode register set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 9: mode register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 10: mode register bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 11: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 12: basic write burst/dm timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 13: write burst basic sequence: bl = 2, rl = 4, wl = 5, configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 14: write burst basic sequence: bl = 4, rl = 4, wl = 5, configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 15: write followed by read: bl = 2, rl = 4, wl = 5, conf iguration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 16: write followed by read: bl = 4, rl = 4, wl = 5, conf iguration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 17: read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 18: basic read burst timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 19: read burst: bl = 2, rl = 4, configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 20: read burst: bl = 4, rl = 4, configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 21: read followed by write, bl = 2, rl = 4, wl = 5, configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 22: read followed by write, bl = 4, rl = 4, wl = 5, co nfiguration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 23: read/write interleave: bl = 4, t rc = 4, wl = 5, configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 24: read/write interleave: bl = 4, t rc = 6, wl = 7, configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 25: read/write interleave: bl = 4, t rc = 8, wl = 9, configuration 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 26: auto refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 27: auto refresh cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 28: on-die termination-equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 29: read burst with odt: bl = 2, configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 30: read nop read with odt: bl = 2, configuration 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 31: read nop nop read with odt: bl = 2, configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 32: command description in multiplexed address mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 33: mode register set command in multiplexed address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 34: power-up sequence in multiplexed address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 35: burst refresh operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 36: write burst basic sequence: bl = 4, with multiplexed addresses, configuration 1, wl = 6 . . . . . .34 figure 37: read burst basic se quence: bl = 4, with multiplexed addresses, configuration 1, rl = 5. . . . . . . .34 figure 38: tap controller state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 39: tap controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 40: tap timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 41: output test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 42: input waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 43: 144-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18clot.fm - rev. f 11/04 en 4 ?2004 micron technology, inc. all rights reserved. list of tables table 1: valid part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 3: address widths at different burst lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 4: command table 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 5: description of commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 6: ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 7: clock input operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 8: rldram configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 9: on-die termination dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 10: address mapping in multiplexed address mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 11: configuration table in multiplexed address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 12: tap ac electrical char acteristics and operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 13: tap ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 14: tap dc electrical characteristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 15: identification register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 16: scan register sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 17: instruction codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 18: boundary scan (exit) order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 19: dc electrical characteristics and operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 20: ac electrical characteristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 21: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 22: i dd operating conditions and maximum limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 5 ?2004 micron technology, inc. all rights reserved. general description the micron ? 288mb reduced latency dram (rldram) ii is a high-speed memory device designed for high bandwidth communication data storage. applications include, but are not limited to, transmit- ting or receiving buffers in telecommunication sys- tems and data or instruction cache applications requiring large amounts of memory. the chip's eight- bank architecture is optimized for high speed and achieves a peak bandwidth of 28.8 gb/s, using two separate 18-bit double data rate (ddr) parts and a maximum system clock of 400 mhz. the ddr separate i/o interface transfers two 18- or 9-bit wide data word per clock cycle at the i/o balls. the read port has dedicated data outputs to support read operations, while the write port has dedicated input balls to support write operations. output data is referenced to the free-running output data clock. this architecture eliminates the need for high-speed bus turnaround. commands, addresses, and control signals are reg- istered at every positive edge of the differential input clock, while input data is registered at both positive and negative edges of the input data clock(s). read and write accesses to the rldram are burst- oriented. the burst length is programmable from 2, 4, or 8 by setting the mode register. the device is supplied with 2.5v and 1.8v for the core and 1.5v or 1.8v for the output drivers. bank-scheduled refresh is supported with row address generated internally. a standard fbga 144-ball package is used to enable ultra high-speed data tr ansfer rates and a simple upgrade path from former products. 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 6 ?2004 micron technology, inc. all rights reserved. figure 2: functional block diagram ? 16 meg x 18 note: 1. when the bl = 8 setting is used, a18 and a19 are ?don?t care.? 2. when bl = 4 setting is used, a19 is ?don?t care.? a0?a19 1, 2 , b0, b1, b2 column address buffer column address counter refresh counter row decoder memory array bank 1 column decoder sense amp and data bus row address buffer row decoder memory array bank 0 column decoder sense amp and data bus row decoder memory array bank 2 column decoder sense amp and data bus row decoder memory array bank 3 column decoder sense amp and data bus row decoder memory array bank 5 column decoder sense amp and data bus row decoder memory array bank 4 column decoder sense amp and data bus row decoder memory array bank 6 column decoder sense amp and data bus row decoder memory array bank 7 column decoder ck ck# dk dk# we# cs# ref# dm v ref sense amp and data bus output data valid qvld output data clock qk[1:0], qk#[1:0] input buffers output buffers control logic and timing generator d0?d17 q0?q17 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 7 ?2004 micron technology, inc. all rights reserved. figure 3: 16 meg x 18 ball assi gnment (top view) 144-ball fbga note: 1. reserved for future use. this may optionally be connected to gnd. 2. reserved for future use. this signal is internally connected and has parasitic ch aracteristics of an address input signal. this may optionally be connected to gnd. 3. no function. this signal is intern ally connected and has parasitic char acteristics of a cl ock input signal. 1 2 3 4 5 6 7 8 9 10 11 12 a v ref v ss v ext v ss v ss v ext tms tck b v dd d4 q4 v ss qv ss q q0 d0 v dd c v tt d5 q5 v dd qv dd q q1 d1 v tt d (a22) 1 d6 q6 v ss qv ss q qk0# qk0 v ss e (a21) 2 d7 q7 v dd qv dd q q2 d2 (a20) 2 f a5 d8 q8 v ss qv ss q q3 d3 qvld g a8 a6 a7 v dd v dd a2 a1 a0 h b2 a9 v ss v ss v ss v ss a4 a3 j nf 3 nf 3 v dd v dd v dd v dd b0 ck k dk dk# v dd v dd v dd v dd b1 ck# l ref# cs# v ss v ss v ss v ss a14 a13 m we# a16 a17 v dd v dd a12 a11 a10 n a18 d14 q14 v ss qv ss q q9 d9 a19 p a15 d15 q15 v dd qv dd q q10 d10 dm r v ss qk1 qk1# v ss qv ss q q11 d11 v ss t v tt d16 q16 v dd qv dd q q12 d12 v tt u v dd d17 q17 v ss qv ss q q13 d13 v dd v v ref zq v ext v ss v ss v ext tdo tdi 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 8 ?2004 micron technology, inc. all rights reserved. figure 4: 32 meg x 9 ball assi gnment (top view) 144-ball fbga note: 1. reserved for future use. th is signal is not connected. 2. reserved for future use. this signal is internally connected and has parasitic ch aracteristics of an address input signal. 3. no function. this signal is intern ally connected and has parasitic char acteristics of a cl ock input signal. 4. do not use. this signal is internally connected and has parasitic char acteristics of a i/ o. this may optionally be connected to gnd. 1 2 3 4 5 6 7 8 9 10 11 12 a v ref v ss v ext v ss v ss v ext tms tck b v dd dnu 4 dnu 4 v ss qv ss q q0 d0 v dd c v tt dnu 4 dnu 4 v dd qv dd q q1 d1 v tt d (a22) 1 dnu 4 dnu 4 v ss qv ss q qk0# qk0 v ss e (a21) 2 dnu 4 dnu 4 v dd qv dd q q2 d2 a20 f a5 dnu 4 dnu 4 v ss qv ss q q3 d3 qvld g a8 a6 a7 v dd v dd a2 a1 a0 h b2 a9 v ss v ss v ss v ss a4 a3 j nf 3 nf 3 v dd v dd v dd v dd b0 ck k dk dk# v dd v dd v dd v dd b1 ck# l ref# cs# v ss v ss v ss v ss a14 a13 m we# a16 a17 v dd v dd a12 a11 a10 n a18 dnu 4 dnu 4 v ss qv ss q q4 d4 a19 p a15 dnu 4 dnu 4 v dd qv dd q q5 d5 dm r v ss dnu 4 dnu 4 v ss qv ss q q6 d6 v ss t v tt dnu 4 dnu 4 v dd qv dd q q7 d7 v tt u v dd dnu 4 dnu 4 v ss qv ss q q8 d8 v dd v v ref zq v ext v ss v ss v ext tdo tdi 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 9 ?2004 micron technology, inc. all rights reserved. table 2: ball descriptions symbol type description ck, ck# input input clock: ck and ck# are differential clock inputs. addresses and commands are latched on the rising edge of ck. ck# is ideally 180 degrees out of phase with ck. cs# input chip select: cs# enables the command decoder when low and disables it when high. when the command decoder is disabled, new commands are ignored, but internal operations continue. we#, ref# input command inputs: sampled at the positive edge of ck, we#, and ref# define (together with cs#) the command to be executed. a[0:20] input address inputs: a[0:20] defi ne the row and column ad dresses for read and write operations. during a mode register set, the address inputs define the register settings. they are sampled at the rising edge of ck. in the x18 configuration, a[20] is reserved for address expansion. these expa nsion addresses can be treated as address inputs, but they do not affect the operation of the device. a21 ? reserved for future use. this signal is in ternally connected and can be treated as an address input. a22 ? reserved for future use. this signal is no t connected and may be connected to ground. dkx, dkx# input input data clock: dkx and dkx# are the differ ential input data clocks. all input data is referenced to both edges of dk. dk# is ideally 180 degrees out of phase with dk. d0? d17 are referenced to dk0 and dk0#. dm input input data mask: the dm signal is the input mask signal for write data. input data is masked when dm is sampled high, along with the write input data. dm is sampled on both edges of dk. ba[0:2] input bank address inputs: select to which internal bank a command is being applied. d0?d17 input data input: the d signals form the 18-bit input data bus. during write commands, the data is referenced to both edges of dk. q0?q17 output data output: the q signals form the 18-bit output data bus. during read commands, the data is referenced to both edges of qk. qkx, qkx# output output data clocks: qkx and qkx# are opposi te polarity, output data clocks. during reads, they are free running and edge-aligned with data output from the rldram. qkx# is ideally 180 degrees out of phase wi th qkx. qk0 and qk0# are aligned with q0? q8 and qk1 and qk1# are aligned with q9?q 17. consult the rldram ii design guide for more details. qvld output data valid: the qvld indicates valid output data. qvld is edge-aligned with qkx and qkx#. tms tdi input ieee 1149.1 test inputs: these balls may be left as no connects if the jtag function is not used in the circuit tck input ieee 1149.1 clock input: this ball must be tied to v ss if the jtag functi on is not used in the circuit. tdo output ieee 1149.1 test output: jtag output. zq input/output external impedance [25 ? ?60 ? ]: this signal is used to tu ne the device outputs to the system data bus impedance. q output impe dance is set to 0.2 x rq, where rq is a resistor from this signal to ground. co nnecting zq to gnd invokes the minimum impedance mode. connecting zq to v dd invokes the maximum impedance mode. refer to figure 10 on page 16 to activate this function. v ref input input reference voltage: nominally v dd q/2. provides a reference voltage for the input buffers. v ext supply power supply: 2.5v nominal. see table 19, dc electrical characte ristics and operating conditions, on page 41 for range. v dd supply power supply: 1.8v nominal. see table 19, dc electrical characte ristics and operating conditions, on page 41 for range. 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 10 ?2004 micron technology, inc. all rights reserved. commands according to the functional signal description, the following command sequences are possible. all input states or sequences not shown are illegal or reserved. all command and address inputs must meet setup and hold times around the rising edge of ck. note: 1. x represents a ?don?t care?; h represents a logic high; l re presents a logic low; a represents a valid address; and ba represents a valid bank address. 2. only a[17:0] are used for the mrs command. 3. see table 3 above. v dd q supply dq power supply: nominally, 1.5v or 1.8v. isolated on the device for improved noise immunity. see table 19: ?dc electrical characteristics and operating conditions? on page 41 for range. v ss supply ground. v ss q supply dq ground: isolated on the device for improved noise immunity. v tt supply power supply: isolated termination supply. nominally, v dd q/2. see table 19, dc electrical characteristics and operating conditions, on page 41 for range. nf ? no function: these balls may be connected to ground. dnu ? do not use: these balls may be connected to ground. table 2: ball descriptions (continued) symbol type description table 3: address widths at different burst lengths burst length configuration x18 x9 bl = 2 19:0 20:0 bl = 4 18:0 19:0 bl = 8 17:0 18:0 table 4: command table 1 operation code cs# we# ref# a(20:0) b(2:0) notes device deselect/no operation desel/nophxxxx mrs: mode register set mrslllopcodex2 read read l h h a ba 3 write write l l h a ba 3 auto refresh aref l h l x ba 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 11 ?2004 micron technology, inc. all rights reserved. note: 1. when the chip is deselected, internal nop comma nds are generated and no commands are accepted. 2. actual refresh is 32ms/8k/8 = 0.488s. 3. actual refresh is 32ms/8k = 3.90s. table 5: description of commands command description desel/nop 1 the nop command is used to perform a no operat ion to the rldram, which essentially deselects the chip. use the nop command to prevent unwanted commands from being registered during idle or wait states. operations already in progress are not affe cted. output values depend on command history. mrs the mode register is set via the address inpu ts a(17:0). see figure 10 on page 16 for further information. the mrs command can only be issued when all banks are idle and no bursts are in progress. read the read command is used to initiate a burst read access to a bank. the value on the ba(2:0) inputs selects the bank, and the address provided on inputs a(20:0) selects th e data location within the bank. write the write command is used to initiate a burst write access to a bank. the value on the ba(2:0) inputs selects the bank, and the address provided on inputs a(20:0) selects th e data location within the bank. input data appearing on the ds is writte n to the memory array su bject to the dm input logic level appearing coincident with the data . if the dm signal is registered low, the corresponding data will be wr itten to memory. if the dm si gnal is registered high, the corresponding data inputs will be ignored (i.e., th is part of the data word will not be written). aref the aref is used during no rmal operation of the rldram to refresh the memory content of a bank. the command is nonpersistent, so it must be issued each time a refres h is required. the value on the ba(2:0) inputs selects th e bank. the refresh address is generated by an internal refresh controller, effectively making each address bit a ?don?t care ? during the aref command. the rldram requires 64k cycles at an average periodic interval of 0.49s 2 (max). to improve efficiency, eight aref co mmands (one for each bank) can be po sted to the rldram at periodic intervals of 3.9s 3 . 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 12 ?2004 micron technology, inc. all rights reserved. note: 1. all timing parameters are measured relative to the crossing point of ck/ck#, dk/dk# and to the crossing point with v ref of the command, address, and data signals. 2. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 3. t qkq0 is referenced to q0?q8 in x18. t qkq1 is referenced to q9?q17 in x18. 4. t qkq takes into account the skew between any qkx and any q. table 6: ac electrical characteristics note 1 description symbol -25 -33 -5 units notes min max min max min max clock clock cycle time t ck, t dk 2.5 5.7 3.3 5.7 5.0 5.7 ns system frequency f ck, f dk 175 400 175 300 175 200 mhz clock phase jitter t ck var 0.15 0.20 0.25 ns 2 clock high time t ckh, t dkh 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low time t ckl, t dkl 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock to input data clock t ckdk -0.3 0.5 -0.3 1.0 -0.3 1.5 ns mode register set cycle time to any command t mrsc 666 t ck setup times address/command and input setup time t as/ t cs 0.4 0.5 0.8 ns data-in and data mask to dk setup time t ds 0.25 0.3 0.4 ns hold times address/command and input hold time t ah/ t ch 0.4 0.5 0.8 ns data-in and data mask to dk hold time t dh 0.25 0.3 0.4 ns data and data strobe output data clock high time t qkh 0.9 1.1 0.9 1.1 0.9 1.1 t ckh output data clock low time t qkl 0.9 1.1 0.9 1.1 0.9 1.1 t ckl qk edge to clock edge skew t ckqk -0.25 0.25 -0.3 0.3 -0.5 0.5 ns qk edge to output data edge t qkq0, t qkq1 -0.2 0.2 -0.25 0.25 -0.3 0.3 ns 3 qk edge to any output data edge t qkq -0.3 0.3 -0.35 0.35 -0.4 0.4 ns 4 qk edge to qvld t qkvld -0.3 0.3 -0.35 0.35 -0.4 0.4 ns 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 13 ?2004 micron technology, inc. all rights reserved. figure 5: clock/input data clock command/address timings initialization the rldram must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined opera- tions or permanent damage to the device. the following sequence is used for power-up: 1. apply power (v ext , v dd , v dd q, v ref , v tt ) and start clock as soon as the supply voltages are sta- ble. apply v dd and v ext before or at the same time as v dd q. apply v dd q before or at the same time as v ref and v tt . although there is no timing relation between v ext and v dd , the chip starts the power-up sequence only after both voltages are at their nominal levels. the pad supply must not be applied before the core supplies. maintain all remaining balls in nop conditions. 2. maintain stable conditions for 200s (min). 3. issue three mrs commands: two dummies plus one valid mrs. 4. t mrsc after the valid mrs, issue eight auto refresh commands, one on each bank and sepa- rated by 2,048 cycles. initial bank refresh order does not matter. 5. after t rc, the chip is ready for normal operation. figure 6: power-up sequence ck# ck t ckh t ckl t ah t as t ck cmd, addr dkx# dkx t ckdk t ckdk don?t care t dkh t dkl t dk valid valid valid v ext v dd v dd q v ref ck# ck cmd 200s min t mrsc t rc 2,048 cycles min 6 2,048 cycles min mrs mrs mrs rf0 rf1 rf7 ac don?t care add v tt nop nop nop mrs: mrs command rfx: refresh bank x ac: any command 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 14 ?2004 micron technology, inc. all rights reserved. programmable impedance output buffer the rldram ii is equipped with programmable impedance output buffers. this allows a user to match the driver impedance to the system. to adjust the impedance, an external precision resistor (rq) is con- nected between the zq ball and v ss . the value of the resistor must be five times the desired impedance. for example, a 300 : resistor is required for an output impedance of 60 : . to ensure that output impedance is one fifth the value of rq (within 15 percent), the range of rq is 125 : to 300 : . output impedance updates may be required because, over time, variations may occur in supply voltage and temperature. the device samples the value of rq. an impedance update is transparent to the sys- tem and does not affect de vice operation. all data sheet timing and current specifications are met during an update. clock considerations the rldram ii utilizes internal delay-locked loops for maximum output, data valid windows. it can be placed into a stopped-cloc k state to minimize power with a modest restart time of 1,024 cycles. 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 15 ?2004 micron technology, inc. all rights reserved. figure 7: clock input note: 1. dkx and dkx# have the same requirements as ck and ck#. 2. all voltages referenced to v ss . 3. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal re ference/supply voltage levels, but the related specifications and device operat ions are tested for the fu ll voltage range specified. 4. outputs (except for i dd measurements) measured with equivalent load. 5. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test envi ronment, but input timing is still refer- enced to v ref (or to the crossing point for ck/ck#), and parameter specifications are tested for the specified ac input levels under normal use conditions. the mi nimum slew rate for the input signals used to test the device is 2 v/ns in the range between v il ( ac ) and v ih ( ac ). 6. the ac and dc input level specifications ar e as defined in the hstl standard (i.e., the receiver will effectively switch as a result of the signal cro ssing the ac input level, and will remain in that state as long as the si gnal does not ring back above [below] the dc in put low [high] level). 7. the ck/ck# input reference level (for timing referenced to ck/ck#) is the poin t at which ck and ck# cross. the input reference level for signals other than ck/ck# is v ref . 8. ck and ck# input slew rate must be t 2 v/ns ( t 4 v/ns if measured differentially). 9. v id is the magnitude of the difference between th e input level on ck and the input level on ck#. 10. the value of v ix is expected to equal v dd q/2 of the transmitting device and must tra ck variations in the dc level of the same. 11. ck and ck# must cross within this region. 12. ck and ck# must meet at least v id ( dc ) min when static and centered around v dd q/2. 13. minimum peak-to-peak swing. table 7: clock input operating conditions notes 1?8 parameter/condition symbol min max units notes clock input voltage level; ck and ck# v in ( dc ) -0.3v dd q + 0.3 v clock input differential voltage; ck and ck# v id ( dc )0.2v dd q + 0.6 v 9 clock input differential voltage; ck and ck# v id ( ac )0.4v dd q + 0.6 v 9 clock input crossing point voltage; ck and ck# v ix ( ac )v dd q/2 - 0.15 v dd q/2 + 0.15 v 10 ck ck# v in(dc) max 11 12 maximum clock level minimum clock level 13 v in(dc) min v dd q/2 v dd q/2 + 0.15 v dd q/2 - 0.15 x v ix(ac) min x v id(ac) v id(dc) v ix(ac) max 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 16 ?2004 micron technology, inc. all rights reserved. mode register set command (mrs) the mode register stores the data for controlling the operating modes of the memory. it programs the rldram configuration, burs t length, test mode, and i/o options. during a mrs command, the address inputs a(17:0) are sampled and stored in the mode reg- ister. t mrsc must be met before any command can be issued to the rldram. the mode register may be set at any time during device operation. however, any pending operations are not guaranteed to successfully complete. see the rldram ii design guide for more details. figure 8: mode register set timing note: mrs: mrs command an d ac: any command. figure 9: mode register set note: cod: code to be load ed into the register. figure 10: mode register bit map note: 1. bits a(17:10) must be set to zero. 2. bl = 8 is not available for configuration 1. 3. 15% temperature variation. ck# ck cmd t mrsc mrs nop nop ac don?t care ck# ck we# ref# a(17:0) cs# cod a(20:18) ba(2:0) don?t care a2 a4 a5 a(17:10) a3 a1 a0 a6 a7 a3 0 1 bl 4 a4 0 1 8 2 0 0 1 1 reserved 1 a9 a7 0 1 a8 a2 a1 a0 10 configuration configuration rldram configuration 1 2 (default) reserved reserved reserved 1 2 not valid 2 (default) dll enabled dll reset dll reset burst length burst length dll reset address mux address mux dll reset (default) 2 3 reserved 10 11 01 01 00 00 1 1 0 0 1 0 1 0 11 impedance matching impedance matching a8 0 1 resistor external internal 50 ? 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 17 ?2004 micron technology, inc. all rights reserved. configuration table table 8 shows, for different operating frequencies, the different rldram configurations that can be pro- grammed into the mode register. the read and write latency ( t rl and t wl) values along with the row cycle times ( t rc) are shown in clock cycles as well as in nanoseconds. the shaded areas correspond to configurations that are not allowed. note: 1. bl = 8 is not available for configuration 1. table 8: rldram configuration table frequency symbol configuration unit 1 1 2 3 t rc 4 6 8 cycles t rl 4 6 8 cycles t wl 5 7 9 cycles 400 mhz t rc 20.0 ns t rl 20.0 ns t wl 22.5 ns 300 mhz t rc 20.0 26.7 ns t rl 20.0 26.7 ns t wl 23.3 30.0 ns 200 mhz t rc 20.0 30.0 40.0 ns t rl 20.0 30.0 40.0 ns t wl 25.0 35.0 45.0 ns 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 18 ?2004 micron technology, inc. all rights reserved. write basic information write accesses are initiated with a write com- mand, as shown in figure 11. row and bank addresses are provided together with the write command. during write commands, data will be registered at both edges of dk according to the programmed burst length (bl). a write latency (wl) one cycle longer than the programmed read latency (rl + 1) is present, with the first valid data registered at the first rising dk edge wl cycles after the write command. any write burst may be followed by a subsequent read command. figures 15 and 16 illustrate the tim- ing requirements for a write followed by a read for bursts of two and four, respectively. setup and hold times for incoming d relative to the dk edges are specified as t ds and t dh. the input data is masked if the corresponding dm signal is high. the setup and hold times for data mask are also t ds and t dh. figure 11: write command note: a: address; ba: bank address. figure 12: basic write burst/dm timing timing parameters ck# ck we# ref# cs# a ba a(20:0) ba(2:0) d dm t dh t ds d0 d1 d2 d3 dkx# dkx t dh t ds t dh t ds don?t care write latency data masked data masked ck# ck t ckdk symbol -25 -33 -5 units min max min max min max t ds 0.25 0.3 0.4 ns t dh 0.25 0.3 0.4 ns t ckdk -0.3 0.5 -0.3 1.0 -0.3 1.5 ns symbol -25 -33 -5 units min max min max min max 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 19 ?2004 micron technology, inc. all rights reserved. figure 13: write burst basic sequence: bl = 2, rl = 4, wl = 5, configuration 1 figure 14: write burst basic sequence: bl = 4, rl = 4, wl = 5, configuration 1 note: 1. a/bax: address a of bank x wr: write command d xy : data y to bank x rc: row cycle time wl: write latency 2. any free bank may be used in any given cmd. the sequ ence shown is only one ex ample of a bank sequence. ck# ck cmd 012345678 addr wl = 5 d d0a d1a d0b d1b d2a d2b d3a d3 wr a ba0 a ba1 a ba2 a ba3 a ba0 a ba4 a ba5 a ba6 a ba7 wr wr wr wr wr wr wr wr dk# dk rc = 4 addr a ba0 a ba1 a ba0 a ba3 a ba0 ck# ck cmd 012345678 wl = 5 d d0a d0c d0b d0d d1a d1b d1c d1 wr nop wr nop wr nop wr nop wr don?t care dk# dk rc = 4 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 20 ?2004 micron technology, inc. all rights reserved. figure 15: write followed by read: bl = 2, rl = 4, wl = 5, configuration 1 figure 16: write followed by read: bl = 4, rl = 4, wl = 5, configuration 1 note: a/bax: address a of bank x wr: write d xy : data y to bank x wl: write latency rd: read qxy: data y from bank x rl: read latency ck# ck cmd 012 34567 89 addr wl = 5 rl = 4 d d0a d0b wr a ba0 a ba1 a ba2 nop rd rd nop nop nop nop nop nop don?t care qkx qkx# q1a q2a q1b q2b q dk# dk ck# ck cmd 012 34567 89 addr wl = 5 rl = 4 d q1a q1c q1b q1d q3a q3b d0a d0b d0c d0d wr a ba0 a ba1 a ba2 nop rd nop rd nop nop nop nop don?t care qkx qkx# q wr d2a d2b d2c d2d q3c q3d a ba3 dk# dk 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 21 ?2004 micron technology, inc. all rights reserved. read basic information read accesses are initiated with a read command, as shown in figure 17. row and bank addresses are provided with the read command. during read bursts, the memory device drives the read data edge-aligned with the qk signal. after a pro- grammable read latency, data is available at the out- puts. the data valid signal in dicates that valid data will be present in the next half clock cycle. the skew between qk and the crossing point of ck is specified as t ckqk. t qkq0 is the skew between qk0 and the last valid data edge considered over all the data generated at the q signals. t qkq1 is the skew between qk1 and the last valid data edge considered over all the data generated at the q signals. t qkqx is derived at each qkx clock edge and is not cumulative over time. t qkq is the maximum of t qkq0 and t qkq1. after completion of a bu rst, assuming no other commands have been initiated, output data (q) will go high-z. back-to-back read commands are possible, producing a continuous flow of output data. the data valid window is derived from each qk transition and is defined as: min ( t qkh, t qkl) - 2( t qkq [max]). any read burst may be followed by a subsequent write command. figures 21 and 22 illustrate the tim- ing requirements for a read followed by a write. figure 17: read command note: a: address; ba: bank address. ck# ck we# ref# cs# a ba a(20:0) ba(2:0) don?t care 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 22 ?2004 micron technology, inc. all rights reserved. figure 18: basic read burst timing timing parameters note: 1. minimum data valid window can be expressed as min ( t qkh, t qkl) - 2 x t qkqx (max). 2. t qkq0 is referenced to q0?q8 in x18. t qkq1 is referenced to q9?q17 in x18. 3. t qkq takes into account the skew between any qkx and any q. undefined t qkvld t qkvld t qkq note 1 t qkq t qkq t ckqk qvld q ck# ck qkx qkx# t ckh t ckl t ck q0 q1 q2 q3 t qkl t qkh symbol -25 -33 -5 units min max min max min max t ck 2.5 5.7 3.3 5.7 5.0 5.7 ns t ckh 0.45 0.55 0.45 0.55 0.45 0.55 t ck t ckl 0.45 0.55 0.45 0.55 0.45 0.55 t ck t ckqk -0.25 0.25 -0.3 0.3 -0.5 0.5 ns t qkq -0.3 0.3 -0.35 0.35 -0.4 0.4 ns t qkq0, t qkq1 -0.2 0.2 -0.25 0.25 -0.3 0.3 ns t qkvld -0.3 0.3 -0.35 0.35 -0.4 0.4 ns t qkh 0.91.10.91.10.91.1 t ckh t qkl 0.91.10.91.10.91.1 t ckl symbol -25 -33 -5 units min max min max min max 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 23 ?2004 micron technology, inc. all rights reserved. figure 19: read burst: bl = 2, rl = 4, configuration 1 figure 20: read burst: bl = 4, rl = 4, configuration 1 note: a/bax: address a of bank x rd: read d xy : data y to bank x rc: row cycle time rl: read latency ck# ck cmd 012345678 addr rc = rl = 4 q qkx qkx# q0a q1a q0b q1b q2a q2b q3a q3b q0a rd a ba0 a ba1 a ba2 a ba3 a ba0 a ba7 a ba6 a ba5 a ba4 rd rd rd rd rd rd rd rd don?t care undefined qvld ck# ck cmd 012345678 addr rc = rl = 4 q qkx qkx# q0a q0c q0b q0d q1a q1b q1c q1d q0a rd a ba0 a ba1 a ba0 a ba1 a ba3 nop rd nop rd nop rd nop rd don?t care undefined qvld 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 24 ?2004 micron technology, inc. all rights reserved. figure 21: read followed by write, bl = 2, rl = 4, wl = 5, configuration 1 figure 22: read followed by write, bl = 4, rl = 4, wl = 5, configuration 1 note: a/bax: address a of bank x wr: write command d xy : data y to bank x wl: write latency rd: read command q xy : data y from bank x rl: read latency ck# ck cmd 01234567 addr rl = 4 qkx qkx# rd a ba0 a ba1 a ba2 wr wr nop nop nop nop nop don?t care wl = 5 q d1a d2a d1b d2b q0a q0b d dk# dk ck# ck cmd 01234567 addr rl = 4 qkx qkx# rd a ba0 a ba1 rd wr nop nop nop nop nop don?t care wl = 5 q d1a d1c d1b d1d q0a q0c q0b q0d d a ba2 q2a q2c q2b dk# dk 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 25 ?2004 micron technology, inc. all rights reserved. figure 23: read/wri te interleave: bl = 4, t rc = 4, wl = 5, configuration 1 figure 24: read/wri te interleave: bl = 4, t rc = 6, wl = 7, configuration 2 note: a/bax: address a of bank x wr: write command d xy : data y to bank x wl: write latency rd: read command qxy: data y from bank x rl: read latency t rc: row cycle time addr ck# ck cmd 012345678 wl = 5 qq0aq0c q0b q0d q2a q2b q2c q2d rd wr rd wr rd wr rd wr rd qkx# qkx rl = 4 wr rd q0b q0a q0c q0d q2a d d1a d1c d1b d1d d3a d3b d3c d3d d1a 9 10 t rc = 4 d a ba0 a ba1 a ba2 a ba3 a ba0 a ba1 a ba2 a ba3 a ba0 a ba1 a ba2 don?t care undefined don?t care undefined addr ck# ck cmd 012345678 wl = 7 q q0a q0c q0b q0d q2a q2b q2c q2d rd wr rd wr rd wr rd wr rd qkx# qkx rl = 6 wr rd q4b q4a q4c q4d q2a d d1a d1c d1b d1d d3a d3b d3c d3d d5a 9 10 t rc = 6 d a ba0 a ba1 a ba2 a ba3 a ba4 a ba5 a ba0 a ba1 a ba2 a ba3 a ba2 12 q0a q0b q0c q0d rd wr rd wr rd q2a d5c d5b d5d d1a 13 14 a ba4 a ba5 a ba0 a ba1 a ba2 11 d1 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 26 ?2004 micron technology, inc. all rights reserved. figure 25: read/wri te interleave: bl = 4, t rc = 8, wl = 9, configuration 3 note: a/bax: address a of bank x wr: write command d xy : data y to bank x wl: write latency rd: read command qxy: data y from bank x rl: read latency t rc: row cycle time 789 15 wl = 9 q0a q0c q0b q0d q2a q2b q2c q2d rd wr rd wr rd wr rd wr rd wr rd q4b q4a q4c q4d q6a d1a d1c d1b d1d d3a d3b d3c d3d d5a 16 17 d a ba7 a ba0 a ba1 a ba2 a ba3 a ba4 a ba5 a ba6 a ba7 a ba0 a ba1 addr ck# ck cmd 012 q rd wr rd qkx# qkx rl = 8 d t rc = 8 a ba0 a ba1 a ba2 10 11 12 13 14 d5c d5b d5d d7a d7b d7c q6b q6c q6d q0b q0a q0c d7 don?t care undefined 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 27 ?2004 micron technology, inc. all rights reserved. auto refresh command (aref) aref is used to perform a refresh cycle on one row in a specific bank. the row addresses are generated by an internal refresh counter for each bank; external address balls are ?don?t care.? the delay between the aref command and a subsequent command to the same bank must be at least t rc. within a period of 32ms ( t ref), the entire memory must be refreshed. figure 27 illustrates an example of a continuous refresh sequence. other refresh strategies, such as burst refresh, are also possible. figure 26: auto refresh command note: ba: bank address. figure 27: auto refresh cycle note: 1. ac x : any command on bank x arf x : auto refresh bank x acy: any command on different bank 2. t rc is configuration-dependent. refer to table 8, rldram configuration table, on page 17. ck# ck we# ref# cs# ba a(20:0) ba(2:0) ck# ck cmd t rc arf x ac y ac x ac y arf x ac y don?t care 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 28 ?2004 micron technology, inc. all rights reserved. on-die termination on-die termination (odt) is enabled by setting a9 to ?1? during an mrs command. with odt on, all the dqs and dm are terminated to v tt with a resistance r tt . the command, address, and clock signals are not terminated. figure 28 below shows the equivalent cir- cuit of a q driver with odt. odts are dynamically switched off during read commands and are designed to be off prior to the rldram driving the bus. similarly, odts are designed to switch on after the rldram has issued the last piece of data. odt at the d inputs and dm are always on. note: 1. all voltages referenced to v ss (gnd). 2. v tt is expected to be set equal to v ref and must track variations in the dc level of v ref . 3. the r tt value is measured at 70c t c . figure 28: on-die termination- equivalent circuit figure 29: read burst with odt: bl = 2, configuration 1 note: a/ba x : address a of bank x rd: read q xy : data y to bank x rl: read latency table 9: on-die termination dc parameters description sym min max units notes termination voltage v tt 0.95 x v ref 1.05 x v ref v1, 2 on-die termination r tt 135 165 : 3 v tt r tt sw driver q ck# ck cmd 012345678 addr rl = 4 q qkx qkx# q0a q1a q0b q1b q2a q2b rd a ba0 a ba1 a ba2 rd rd nop nop nop nop nop nop don?t care undefined odt odt on qvld odt off odt on 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 29 ?2004 micron technology, inc. all rights reserved. figure 30: read nop read with odt: bl = 2, configuration 1 figure 31: read nop nop read with odt: bl = 2, configuration 1 note: a/ba x : address a of bank x rd: read q xy :data y to bank x rl: read latency ck# ck cmd 012345678 addr rl = 4 q qkx qkx# q0a q0b q2a q2b rd a ba0 a ba2 nop rd nop nop nop nop nop nop don?t care undefined odt odt on qvld odt on odt off odt off odt on ck# ck cmd 012345678 addr rl = 4 q qkx qkx# q0a q0b q2a q2b rd a ba0 a ba2 nop nop rd nop nop nop nop nop don?t care undefined odt odt on qvld odt on odt off odt off odt on 9 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 30 ?2004 micron technology, inc. all rights reserved. operation with multiplexed addresses in multiplexed address mode, the address can be provided to the rldram in two parts that are latched into the memory with two consecutive rising clock edges. this provides the advantage that a maximum sp of 11 address balls are required to control the rldram, reducing the number of balls on the control- ler side. the bank addresses are delivered to the rldram at the same time as the write command and the first address part, ax. this option is available by setting bit a5 to ?1? in the mode register. once this bit is set, the read, write, and mrs commands follow the format described in figure 32. see figure 34 on page 31 for the power-up sequence. figure 32: command descriptio n in multiplexed address mode note: 1. ax, ay: address ba: bank address 2. the minimum setup and hold times of the two address parts are defined t as and t ah. ck# ck we# ref# cs# ax ba a<20:0> ba<2:0> read ay ax ba write ay ax ba don?t care mrs ay 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 31 ?2004 micron technology, inc. all rights reserved. figure 33: mode regi ster set command in mu ltiplexed address mode the addresses a0, a3, a4, a5, a8, and a9 must be set as follows in order to activate the mode register in the multiplexed address mode. note: 1. bits a(17:10) must be set to zero. 2. bl = 8 is not available for configuration 1. 3. 15% temperature variation. figure 34: power-up sequenc e in multiplexed address mode the following sequence must be respected in order to power up the rldram in the multiplexed address mode. note: 1. address a5 must be set high (muxed address mode sett ing when rldram is in normal mode of operation). 2. address a5 must be set high (muxed address mode se tting when rldram is already in muxed address mode). a4 a5 a4 a3 a3 a0 a8 a9 a3x 0 1 bl 4 a4x 0 1 8 2 0 0 1 1 a9 a9y 0 1 a8 a4y a3y a0x 10 configuration configuration rldram configuration 1 2 (default) reserved reserved reserved 1 2 not valid 2 (default) dll enabled dll reset dll reset burst length burst length dll reset address mux address mux dll reset (default) 2 3 reserved 10 11 01 01 00 00 1 1 0 0 1 0 1 0 11 impedance matching impedance matching a8x 0 1 resistor external a5x 0 1 nonmultiplexed (default) address multiplexed a9x 0 1 enabled termination disabled (default) on-die termination on-die termination unused ax ay internal 50 ? 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 32 ?2004 micron technology, inc. all rights reserved. address mapping the address mapping is described in table 10 as a function of data width and burst length. note: 1. x means ?don?t care.? 2. reserved for a20 expans ion in multiplexed mode. 3. reserved for a21 expans ion in multiplexed mode. table 10: address mapping in multiplexed address mode note 1 data width burst length ball addresses a0 2 a3 a4 a5 3 a8 a9 a10 a13 a14 a17 a18 x18bl = 2axa0a3a4a5a8a9a10a13a14a17a18 ay x a1 a2 x a6 a7 a19 a11 a12 a16 a15 bl = 4axa0a3a4a5a8a9a10a13a14a17a18 ay x a1 a2 x a6 a7 x a11 a12 a16 a15 bl = 8axa0a3a4a5a8a9a10a13a14a17x ay x a1 a2 x a6 a7 x a11 a12 a16 a15 x9bl = 2axa0a3a4a5a8a9a10a13a14a17a18 ay a20 a1 a2 x a6 a7 a19 a11 a12 a16 a15 bl = 4axa0a3a4a5a8a9a10a13a14a17a18 ay x a1 a2 x a6 a7 a19 a11 a12 a16 a15 bl = 8axa0a3a4a5a8a9a10a13a14a17a18 ay x a1 a2 x a6 a7 x a11 a12 a16 a15 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 33 ?2004 micron technology, inc. all rights reserved. configuration table in this mode, the read and write latencies are increased by one clock cycle. the rldram cycle time remains the same, as described in table 11. note: 1. bl = 8 is not available for configuration 1. refresh command in multiplexed address mode similar to other commands, the refresh command is executed on the next rising clock edge when in the multiplexed address mode. however, since only bank address is required for aref, the next command can be applied on the following clock. the operation of the aref command and any other command is repre- sented in figure 35. figure 35: burst refresh operation note: aref: auto refresh ac: any command a x : first part a x of address a y : second part a y of address ba k : bank k ; k is chosen so that t rc is met table 11: configuration table in multiplexed address mode configuration frequency symbol 1 1 2 3 unit t rc 468cycles t rl 579cycles t wl 6810cycles 400 mhz t rc 20.0 ns t rl 22.5 ns t wl 25.0 ns 300 mhz t rc 20.0 26.7 ns t rl 23.3 30.0 ns t wl 26.7 33.3 ns 200 mhz t rc 20.0 30.0 40.0 ns t rl 25.0 35.0 45.0 ns t wl 35.0 40.0 50.0 ns addr ck# ck cmd 012345678 ac aref aref aref aref aref aref aref don?t care aref 9 10 ax ay ac ax ay 11 baddr bak ba0 ba1 ba2 ba3 ba4 ba5 ba6 ba7 bak 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 34 ?2004 micron technology, inc. all rights reserved. figure 36: write burst basic sequenc e: bl = 4, with multiplexed addresses, configuration 1, wl = 6 figure 37: read burst basic sequence: bl = 4, with multiplexed addresses, configuration 1, rl = 5 note: a x /ba k : address a x of bank k a y : address a y of bank k wr: write djk: data k to bank j wl: write latency qjk: data k to bank j rd: read rl: read latency ck# ck cmd 012345678 addr wl = 6 d d0a d0c d0b d0d d1a d1 wr ax ba0 ay ax ba1 ay ax ba2 ay ax ba3 ay ax ba0 nop wr nop wr nop wr nop wr dkx# dkx undefined ck# ck cmd 012345678 addr rl = 5 q qkx qkx# q0a q0c q0b q0d q1a q1b q1c rd nop rd nop rd nop rd nop rd don?t care ax ba0 ay ax ba1 ay ax ba2 ay ax ba0 ay ax ba1 qvld 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 35 ?2004 micron technology, inc. all rights reserved. ieee 1149.1 serial bo undary scan (jtag) rldram incorporates a serial boundary scan test access port (tap). this port operates in accordance with ieee standard 1149.1-2001. the tap operates using logic levels associated with the v dd q supply. rldram contains a tap controller, instruction reg- ister, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate rldram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state, which will not interfere with the opera- tion of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for in formation on loading the instruction register, see figure 38. tdi is internally pulled up and can be unconne cted if the tap is unused in an application. tdi is connected to the most signifi- cant bit (msb) of any register (see figure 39). test data-out (tdo) the tdo output ball is used to serially clock data- out from the registers. the output is active depending upon the current state of the tap state machine (see figure 38). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register (see figure 39). figure 38: tap controller state diagram figure 39: tap controller block diagram note: x = 112 for all configurations. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the rldram and may be performed while the rldram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 bypass register 0 instruction register 0 1 2 3 4 5 6 7 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry selection circuitry tck tms tap controller tdi tdo 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 36 ?2004 micron technology, inc. all rights reserved. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the rldram test circuitry. only one register can be selected at a time throug h the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the fall- ing edge of tck. instruction register eight-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo ball, as shown in figure 39. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as describe d in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board- level serial test data path. bypass register to save time when serially shifting data through reg- isters, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the rldram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the rldram. several balls are also included in the scan register to reserved balls. the rldram has a 113-bit register. the boundary scan register is loaded with the con- tents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the boundary scan order tables (see page 40) show the order in which the bits are connected. each bit cor- responds to one of the balls on the rldram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32- bit code during the capture-dr state when the idcode command is loaded in the instruction regis- ter. the idcode is hardwired into the rldram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification reg- ister definitions table. tap instruction set overview many different instructions (28) are possible with the eight-bit instruction r egister. all used combina- tions are listed in table 17, instruction codes, on page 39. these six instructions are described in detail below. the remaining instructions are reserved and should not be used. the tap controller used in this rldram is fully compliant to the 1149.1 convention. instructions are loaded in to the tap controller dur- ing the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction regis- ter through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest the extest instruction allows circuitry external to the component package to be tested. boundary-scan register cells at output balls are used to apply a test vector, while those at input balls capture test results. typically, the first test vector to be applied using the extest instruction will be shifted into the boundary scan register using the preload instruction. thus, during the update-ir state of extest, the output driver is turned on and the preload data is driven onto the output balls. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. high-z the high-z instruction causes the boundary scan register to be connected between the tdi and tdo. this places all rldram ou tputs into a high-z state. 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 37 ?2004 micron technology, inc. all rights reserved. clamp when the clamp instruction is loaded into the instruction register, the data driven by the output balls are determined from the values held in the boundary scan register. sample/preload when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 50 mhz, while the rldram clock oper ates significantly faster. because there is a large difference between the clock frequencies, it is possible that during the capture-dr state, an input or output wi ll undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be cap- tured. repeatable results may not be possible. to ensure that the boundary scan register will cap- ture the correct value of a signal, the rldram signal must be stabilized long enough to meet the tap con- troller?s capture setup plus hold time (tcs plus tch). the rldram clock input might not be captured cor- rectly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# cap- tured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between tdi and tdo. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions. figure 40: tap timing table 12: tap ac electrical charac teristics and operating conditions +0c = tc = +95c; +1.7v = v dd = +1.9v, unless otherwise noted description conditions symbol min max units notes input high (logic 1) voltage v ih v ref + 0.3 v dd + 0.3 v1, 2 input low (logic 0) voltage v il v ss q - 0.3 v ref - 0.3 v1, 2 t tlth test clock (tck) 123456 test mode select (tms) t thtl test data-out (tdo) t thth test data-in (tdi) t thmx t mvth t thdx t dvth t tlox t tlov don?t care undefined 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 38 ?2004 micron technology, inc. all rights reserved. note: 1. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. note: 1. all voltages referenced to v ss (gnd). 2. overshoot: v ih ( ac ) d v dd + 0.7v for t d t ck/2. undershoot: v il ( ac ) t -0.5v for t d t ck/2. during normal operation, v dd q must not exceed v dd . table 13: tap ac electrical characteristics note 1; +0c d t c d +95c; +1.7v d v dd d +1.9v description symbol min max units clock clock cycle time t thth 20 ns clock frequency f tf 50 mhz clock high time t thtl 10 ns clock low time t tlth 10 ns output times tck low to tdo unknown t tlox 0ns tck low to tdo valid t tlov 10 ns tdi valid to tck high t dvth 5ns tck high to tdi invalid t thdx 5ns setup times tms setup t mvth 5ns capture setup t cs 5ns hold times tms hold t thmx 5ns capture hold t ch 5ns table 14: tap dc electrical charac teristics and operating conditions +0c d t c d +95c; +1.7v d v dd d +1.9v, unless otherwise noted description conditions symbol min max units notes input high (logic 1) voltage v ih v ref + 0.15 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il v ss q - 0.3 v ref - 0.15 v 1, 2 input leakage current 0v d v in d v dd il i -5.0 5.0 a output leakage current output disabled, il o -5.0 5.0 a 0v d v in d v dd q output low voltage i olc = 100a v ol 10.2v1 output low voltage i olt = 2ma v ol 20.4v1 output high voltage |i ohc | = 100a v oh 1v dd q - 0.2 v 1 output high voltage |i oht | = 2ma v oh 2v dd q - 0.4 v 1 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 39 ?2004 micron technology, inc. all rights reserved. table 15: identification register definitions instruction field all devices description revision number (31:28) abcd ab = die revision cd = 10 for x36, 01 for x18, 00 for x9. device id (27:12) 00jkidef10100111 def = 000 for 288m, 001 for 576m, 010 for 1g. i = 0 for common i/o, 1 for separate i/o. jk = 00 for rldram, 01 for rldram ii. micron jedec id code (11:1) 00000101100 allows unique identification of rldram vendor. id register presence indicator (0) 1 indicates the presence of an id register. table 16: scan register sizes register name bit size instruction 8 bypass 1 id 32 boundary scan 113 table 17: instruction codes instruction code description extest 0000 0000 captures i/o ring contents. places the bo undary scan register between tdi and tdo. this operation does not affect rldram operations. id code 0010 0001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect rldram operations. sample/preload 0000 0101 captures i/o ring contents. places the bo undary scan register between tdi and tdo. clamp 0000 0111 selects the bypass register to be connected between tdi and tdo. data driven by output balls are determined from values held in the boundary scan register. high-z 0000 0011 selects the bypass register to be connec ted between tdi and tdo. all outputs are forced into high impedance state. bypass 1111 1111 places the bypass register between tdi an d tdo. this operation does not affect rldram operations. 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 40 ?2004 micron technology, inc. all rights reserved. note: 1. any unused balls that are in the order wi ll read as the logic level applied to the ball site. if left floating, a value of ?0 ? is returned. table 18: boundary scan (exit) order bit# fbga ball bit# fbga ball bit# fbga ball 1 k1 39 r11 77 c11 2 k2 40 r11 78 c11 3 l2 41 p11 79 c10 4 l1 42 p11 80 c10 5 m1 43 p10 81 b11 6 m3 44 p10 82 b11 7m245n1183b10 8n146n1184b10 9p147n1085b3 10 n3 48 n10 86 b3 11 n3 49 p12 87 b2 12 n2 50 n12 88 b2 13 n2 51 m11 89 c3 14 p3 52 m10 90 c3 15 p3 53 m12 91 c2 16 p2 54 l12 92 c2 17 p2 55 l11 93 d3 18 r2 56 k11 94 d3 19 r3 57 k12 95 d2 20 t2 58 j12 96 d2 21 t2 59 j11 97 e2 22 t3 60 h11 98 e2 23 t3 61 h12 99 e3 24 u2 62 g12 100 e3 25 u2 63 g10 101 f2 26 u3 64 g11 102 f2 27 u3 65 e12 103 f3 28 v2 66 f12 104 f3 29 u10 67 f10 105 e1 30 u10 68 f10 106 f1 31 u11 69 f11 107 g2 32 u11 70 f11 108 g3 33 t10 71 e10 109 g1 34 t10 72 e10 110 h1 35 t11 73 e11 111 h2 36 t11 74 e11 112 j2 37 r10 75 d11 113 j1 38 r10 76 d10 ? ? 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 41 ?2004 micron technology, inc. all rights reserved. absolute maximum ratings* storage temperature . . . . . . . . . . . . . . . .-55c to +150c i/o voltage . . . . . . . . . . . . . . . . . . . . -0.3v to v dd q + 0.3v voltage on v ext supply relative to v ss . . . . . . . . . . . . . . . . . . . . . -0.3v to +2.8v voltage on v dd supply relative to v ss . . . . . . . . . . . . . . . . . . . . . -0.3v to +2.1v voltage on v dd q supply relative to v ss . . . . . . . . . . . . . . . . . . . . . -0.3v to +2.1v junction temperature** . . . . . . . . . . . . . . . . . . . . . . .110c *stresses greater than those listed may cause per- manent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect reliability. **junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow. note: 1. all voltages referenced to v ss (gnd). 2. typically the value of v ref is expect to be 0.5 x v dd q of the transmitting device. v ref is expected to track variations in v dd q. 3. peak-to-peak ac noise on v ref must not exceed 2% v ref (dc). 4. overshoot: v ih ( ac ) d v dd + 0.7v for t d t ck/2. undershoot: v il ( ac ) t -0.5v for t d t ck/2. during normal operation, v dd q must not exceed v dd . control input signal s may not have pulse widths less than t ck/2 or operate at frequencies exceeding t ck (max). 5. v dd q can be set to a nominal 1.5v + 0.1v or 1.8v + 0.1v supply 6. i oh and i ol are defined as absolute values and are measured at v dd q/2. i oh flows from the device, i ol flows into the device. 7. if mrs bit a8 is 0, use rq = 250 : in the equation in lieu of presence of an external impedance matched resistor. 8. v ref is expected to equal v dd q/2 of the transmitting device and to track vari ations in the dc level of the same. peak-to- peak noise (non-common mode) on v ref may not exceed 2% of th e dc value. thus, from v dd q/2, v ref is allowed 2%v dd q/2 for dc error and an additional 2%v dd q/2 for ac noise. this measurement is to be taken at the nearest v ref bypass capacitor. 9. v tt is expected to be set equal to v ref and must track variations in the dc level of v ref . 10. on-die termination may be selected using mode regist er bit 9 (see figure 10 on page 16). a resistance r tt from each data input signal to the nearest v tt can be enabled. r tt = 150 : ( 10%) at 70c t c . 11. for v ol and v oh , refer to the spice model fro the rldram ii command driver. table 19: dc electrical characte ristics and operating conditions (+0c d t c d +95c; +1.7v d v dd d +1.9v, unless otherwise noted) description conditions symbol min max units notes supply voltage v ext 2.38 2.63 v 1 supply voltage v dd 1.7 1.9 v 1, 4 isolated output buffer supply v dd q 1.4 vdd v 1, 4, 5 reference voltage v ref 0.49 x v dd q 0.51 x v dd qv 1?3, 8 termination voltage v tt 0.95 x v ref 1.05 x v ref v9, 10 input high (logic 1) voltage v ih v ref + 0.1 v dd q + 0.3 v 1, 4 input low (logic 0) voltage v il v ss q - 0.3 v ref - 0.1 v 1, 4 output high current v oh = v dd q/2 i oh (v dd q/2) / (1.15 x rq/5) (v dd q/2) / (0.85 x rq/5) ma 6, 7, 11 output low current v ol = v dd q/2 i ol (v dd q/2) / (1.15 x rq/5) (v dd q/2) / (0.85 x rq/5) ma 6, 7, 11 clock input leakage current 0v d v in d v dd i lc -5 5 a input leakage current 0v d v in d v dd i li -5 5 a output leakage current 0v d v in d v dd qi lo -5 5 a reference voltage current i ref -5 5 a 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 42 ?2004 micron technology, inc. all rights reserved. figure 41: output test condit ions figure 42: input waveform table 20: ac electrical characte ristics and operating conditions +0c d t c d +95c; +1.7v d v dd d +1.9v, unless otherwise noted description conditions symbol min max units input high (logic 1) voltage matched impedance mode v ih v ref + 0.2 v dd q + 0.3 v input low (logic 0) voltage matched impedance mode v il v ss q - 0.3 v ref - 0.2 v table 21: capacitance description conditions symbol min max units address/control in put capacitance t a = 25c; f = 1 mhz c i 1.5 2.5 pf input/output capacitance (d and q) c o 3.5 5.0 pf clock capacitance c ck 2.0 3.0 pf 10pf dq 50 ? 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 43 ?2004 micron technology, inc. all rights reserved. ta b l e 22 : i dd operating conditions and maximum limits +0c d tc d +95c; +1.7v d v dd d +1.9v, unless otherwise note. description conditions symbol max unit -25 -33 -5 standby current t ck = idle all banks idle, no inputs toggling i sb 1 (v dd ) 48 48 48 ma i sb 1 (v ext ) 26 26 26 active standby current t ck = min, cs# = 1 no commands, address/data change up to once every four clock cycles i sb 2 (v dd ) 288 288 288 ma i sb 2 (v ext ) 26 26 26 incremental current bl = 2, t ck = min, t rc = min, 1 bank active, half address changes once per t rc, read followed by write sequence i dd 1 (v dd ) 348 305 255 ma i dd 1 (v ext ) 41 36 36 incremental current bl = 4, t ck = min, t rc = min, 1 bank active, half address changes once per t rc, read followed by write sequence i dd 2 (v dd ) 352 319 269 ma i dd 2 (v ext ) 48 42 42 incremental current bl = 8, t ck = min, t rc = min, 1 bank active, half address changes once per t rc, read followed by write sequence i dd 3 (v dd ) 408 368 286 ma i dd 3 (v ext ) 55 48 48 burst refresh current t ck = min, t rc = min cyclic bank refresh, data inputs are switching i ref 1 (v dd ) 680 530 367 ma i ref 1 (v ext ) 133 111 105 distributed refresh current t ck = min, t rc = min single bank refresh, half address/data toggle i ref 2 (v dd ) 325 267 221 ma i ref 2 (v ext ) 48 42 42 operating supply current example bl = 2, t ck = min, t rc = min, cyclic bank access, half of address bits change every clock cycle, continuous data i dd 2 w (v dd ) 970 819 597 ma i dd 2 w (v ext ) 100 90 69 operating supply current example bl = 4, t ck = min, t rc = min, cyclic bank access, half of address bits change every two clock cycles, continuous data i dd 4 w (v dd ) 779 609 439 ma i dd 4 w (v ext ) 65 55 44 operating supply current example bl = 8, t ck = min, t rc = min, cyclic bank access, half of address bits change every four clock cycles, continuous data i dd 8 w (v dd ) 668 525 364 ma i dd 8 w (v ext ) 60 51 40 16 meg x 18, 32 meg x 9 2.5v v ext , 1.8v v dd , hstl, sio, rldram ii pdf: 09005aef80a41b59/zip: 09005aef811ba111 micron technology, inc., reserves the right to change products or specifications without notice. mt49h8m18c_2.fm - rev. f 11/04 en 44 ?2004 micron technology, inc. all rights reserved. ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www .micron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. rldram is a trademark of infineon technologies ag in various countries, and is used by micron under license from infineon. all other trademarks are the property of their respective owners. figure 43: 144-ball fbga note: 1. all dimensions in millimeters. data sheet designation no marking: this data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. although c onsidered final, these specifications are subject to change, as further product development an d data characterization sometimes occur. ball a1 id 17.90 ctr 0.555 0.050 0.39 0.05 0.125 0.025 ball a1 id 0.10 c c seating plane 10o typ 0.05 max 10.70 ctr 11.00 0.10 4.40 0.05 5.50 0.05 8.80 2.40 ctr 0.80 typ 1.00 typ 9.25 0.05 8.50 0.05 17.00 18.50 0.10 144x ? |
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